The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each new generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
During the manufacture of various types of monolithic ICs, such as high density metal oxide semiconductor field effect transistor (MOSFET) devices or complementary MOSFETS (CMOS) devices, having several thousand transistors fabricated in a single chip of silicon, there are many stages in a wafer processing sequence where it is desirable to provide a gate dielectric (a layer of a selected dielectric insulating material such as silicon dioxide, SiO2, or silicon nitride, Si3N4, or a high-k material) to function as an insulating layer between a semiconductor substrate and a gate electrode.
Various materials have been used for the gate electrode and gate dielectric in field effect transistors (FET). One approach is to fabricate these devices with a polysilicon or metal material for the gate electrode. Depending upon the device desired to be fabricated, such as an analog or digital device, different gate dielectric layers comprised of different materials and having different thicknesses may be desired. Accordingly, for various devices fabricated over different regions of a semiconductor substrate, flexibility in the material and thickness of the device gate dielectric is desirable.